鎖相迴路設計與應用
Phase Locked Loop Design and Applications
| 節 | 週四 |
|---|---|
2 09:00–09:50 | 鎖相迴路設計與應用 ED220（光復） 3 節連堂 |
3 10:10–11:00 | |
4 11:10–12:00 |
* 根據陽明交大上課時間表所列
This course introduces theories and integrated circuit design techniques of phase-locked (PLL) and delay locked (DLL) loops, from devices to system levels. The applications of PLLs and DLLs in monolithic frequency synthesizer and serial link data transceivers will also be covered and emphasized
Microelectronics, Analog circuit design
無備註
教師未提供此項資料
Approximately : Homework 20 %, Project 10 %, Midterm 35%, Final 35%,
教師未提供此項資料
| 週次 | 主題 |
|---|---|
| 第 1 週 | Introduction |
| 第 2 週 | Overview of PLL applications |
| 第 3 週 | Linear model |
| 第 4 週 | Sub circuits-Phase frequency detector |
| 第 5 週 | Sub circuits - charge pump |
| 第 6 週 | Spring Break |
| 第 7 週 | Frequency divider |
| 第 8 週 | Voltage controlled oscilllator |
| 第 9 週 | Midterm exam |
| 第 10 週 | Noise Analysis of PLLs |
| 第 11 週 | Frequency synthesizer |
| 第 12 週 | Multiplied Delay Locked Loop |
| 第 13 週 | Deskew Buffers |
| 第 14 週 | Clock and data recovery |
| 第 15 週 | Serdes |
| 第 16 週 | All digital PLL (I) |
| 第 17 週 | All digital PLL (II) |
| 第 18 週 | Final term report |
Behzad Razavi, “ Design of Integrated Circuits for Optical Communications”, McGraw Hill, 2003. Floyed M. Garder, “ Phaselock Techniques,” 2nd edition, John Wiley and Sons, 1979. Roland E. Best, “ Phase Locked Loops,” 2nd Edition, McGraw-Hill, Inc. 1993. Dan H. Wolaver, “Phase-Locked Loop Circuits Design,” Prentice-Hall, Inc. 1991. Behzad Razavi, “ Phase-Locking in High-Performance Systems – from devices to architectures”, IEEE press, 2003.
- 地點
- ED 643
- 時間
- By appointment
- 聯絡方式
- By E-mail