進階可程式邏輯系統設計與應用
Advanced Programmable Logic System Design and Application
| 節 | 週一 |
|---|---|
5 13:20–14:10 | 進階可程式邏輯系統設計與應用 EE634（光復） 2 節連堂 |
6 14:20–15:10 | |
A 18:30–19:20 | 進階可程式邏輯系統設計與應用 EE634（光復） 3 節連堂 |
B 19:30–20:20 | |
C 20:30–21:20 |
* 根據陽明交大上課時間表所列
This course is teaching students with or without the basic FPGA knowledge to accomplish a digital system for control, communication, bioelectrical and other applications. Students must design a special project using FPGA, ARM, uProcessor or combinations to design an unique task. All arts will be encouraged to attend the international FPGA technology competition.
Logic Design or Digital System
無備註
2-hr lecture and 3-hr lab every week. The PPT file and experiment both will be adopted for the explanation the content in the textbook.
(a) 10 Experiments: (10X10)X0.5=50% (b) A midterm exam is 10% (c) Final project demonstration including implementation, presentation, report and Innovation : 40% The final score is represented by 0-100 grading.
教師未提供此項資料
| 週次 | 主題 |
|---|---|
| 第 1 週 | 1st - 13th weeks: 2 hr/w Basic Concept & 3hr/w experiments 14th week: Midterm Exam. 15th - 18th weeks: Project Implement Detail information please refers E3 website. |
1. C. H. Roth, L. K. John and B. K. Lee, “Digital Systems Design Using Verilog,”Cengage Learning , 2014 2.Terasic DE1-SOC technology manual
- 地點
- EE740 EE814
- 時間
- (1) Mon. A, B, C, D, E, F, G : 歐陽盟, oym@cn.nctu.edu.tw (2) Mon. A, B, C, D, E, F, G : 顏永哲, yanjohn888@gmail.com
- 聯絡方式
- ext.31965 ext.54415