8/24 – 9/18

115-1 選課時程

進行中

  • 初選第一階段 6/15 – 6/18
  • 初選第二階段 6/22 – 6/25
  • 校際選修 進行中 8/24 – 9/18
  • 初選第三階段 8/31 – 9/3
  • 開學後加退選 9/7 – 9/21
  • 逾期加退選 9/21 – 9/24
選課資源

加入行事曆

選擇訂閱 Google Calendar,或下載通用的 ICS 檔案。

使用 Google Calendar 時,Google 會收到這份課表的公開連結。

通訊系統晶片設計

Chip Design for Communication Systems

學期
106-2
學分
0 學分
當期課號
5048
永久課號
ICN5412
開課單位
電控工程研究所
授課教師
蔡尚澕
校區
光復
類別
選修
上課時間表
週一
5
13:20–14:10
通訊系統晶片設計
EE118(光復)
3 節連堂
6
14:20–15:10
7
15:30–16:20

* 根據陽明交大上課時間表所列

概述

* Understand how digital signal processing techniques can be used in VLSI design * To be familiar with algorithm development and architecture design for base band communication ICs * Understand how to realize the theoretical results to practical applications in standards * Part I: Digital filtering in hardware ■ Interation bound ■ Pipelining and parallel processing ■ Retiming ■ Unfolding ■ Numerical Strength Reduction ■ Multirate signal processing * Part II Communication systems ■ Wireless communication channel model ■ OFDM systems ■ Synchronization ■ MIMO systems ■ MIMO Precoding ■ FFT & CORDIC ■ Channel coding

先修科目

* It is recommended that students have background in digital signal processing and digital communications (Not mandatory) * Some homework may need the use of Matlab and Verilog - TAs will allocate time to teach Verilog and design tools

備註

無備註

教學方式

教師未提供此項資料

評分方式

* Course style - The course will be presented using slides - Some homeworks require the use of Matlab and Verilog (TA will allocate time to teach Verilog and the corresponding tools) * Grading - Homework 30% (5-6 homeworks) - Midterm project 30% - Final project with presentation 40%

課程大綱

教師未提供此項資料

週次計畫

教師未提供此項資料

教科書

* Textbook: -“VLSI Digital Signal Processing Systems: Design and Implementation,” by Keshab K. Parhi ■ * References: -“Digital Signal Processing,” by A. V. Oppenheim and R. W. Schafer, Prentice Hall -“Digital Communications,” by J. G. Proakis, McGraw-Hill - Papers from IEEE

Office Hours
地點
教師未提供此項資料
時間
教師未提供此項資料
聯絡方式
教師未提供此項資料