矽奈米元件及物理

The major subjects provided by this course will cover (1) Si CMOS scaling limitations and the physics in nanoscale (2) Si CMOS device design challenges due to scaling limitations (3) The solutions to extend Si CMOS technology in nanoscale era – new materials, new structures, and integration methods, targeted for devices an integrated ciruts. The major goal of this course aims at providing fundamental knowledge in nanoscale devices and most advanced technologies in nanoscale process integration for integrated circuits. The ultimate goal is to bring up the knowledge base of students in device physics, process integration, and material science, and further stimulate novel ideas and methods in realizing tremendous breakthrough in nanoscale electronics.

Semiconductor device physics, Modern physics, Semiconductor integrated circuit technology

無備註

TA : 周書緯 /chousw0804@gmail.com/0988-811-530 韋安迪Adhi Cahyo Wijaya/adhi.eed07g@nctu.edu.tw/0905032467

CreditMid-term exam. 40% Final exam. (or report)40% Class participation & quiz 20%

• Chapter-1
• Chapter-2
• Chapter-3
• Chapter-4

Research Journals (IBM, Intel) IEEE Journal on NanotechnologyIEEE Proceedings, TED, EDLIEEE Conferences, IEDM, VLSI, SSDMNanoScience, Science & Nature, etc.

地點

教師未提供此項資料

時間

Bi-weekly

聯絡方式

adhi.eed07g@nctu.edu.tw