超大型積體電路量產可行性設計

本課程包含超大型積體電路量產可行性設計的基本概念與實際運用,尤其介紹先進製程所需考慮的製造變異與良率下降因素,以及如何在電路實體設計時考量各種因素,進一步有效分析、模擬及提升可靠度。

Circuit and electronic background courses, VLSI Design

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Lab and HW: 40% Final Project: 30% Tests: Midterm 30%

• 1. Overview of key technologies and EDA methodologies for sub-90nm technologies 2. Variability mismatch sources and design for variability (DFV) 3. Silicon test and measurement for statistical process data 4. Yield degrading factor; DFM includes DFY, DFV, and design for reliability (DFR) 5. Statistical extraction and chip timing impact 6. Manufacturing simulations and analyses for lithography and shape 7. Manufacturing simulations and analyses for thickness and critical defecting area 8. Manufacturability-oriented EDA (placement, routing, and post-route optimization)

References: 1. B.P. Wong et.al., “Nano-CMOS Design for Manufacturability,” Wiley 2009 2. C. Chiang and J. Kawa, “Design for Manufacturability and Yield for Nano-Scale CMOS,” Springer 2007

地點

ED 407

時間

TBD

聯絡方式

hmchen@mail.nctu.edu.tw