數位電路設計
Digital Circuit Design
學期
112-2
學分
0
學分
當期課號
515504
永久課號
CSCS10005
開課單位
資訊學院共同課程
授課教師
蔡孟勳
校區
光復
類別
必修
上課時間表
| 節 | 週三 | 週五 |
|---|---|---|
3 10:10–11:00 | 數位電路設計 ED117（光復） 2 節連堂 | |
4 11:10–12:00 | ||
7 15:30–16:20 | 數位電路設計 ED117（光復） |
* 根據陽明交大上課時間表所列
概述
This course aims to introduce the fundamental concepts, methods and tools of logic design and digital circuits. .
先修科目
教師未提供此項資料
備註
無備註
教學方式
Please refer to the announcement on the E3 platform.
評分方式
Lab 1: 5% Lab 2: 5% Lab 3: 5% Exam 1: 30% Exam 2: 30% Exam 3: 30% (Total: 105%)
課程大綱
- Boolean Algebra and Logic Gates
- Gate-Level Minimization
- Combinational Logic
- Synchronous Sequential Logic
- Registers and Counters
- Memory and Programmable Logic
- Digital Systems and Binary Numbers
週次計畫
| 週次 | 主題 |
|---|---|
| 第 1 週 | Syllabus / Chapter 1 Digital Systems and Binary Numbers |
| 第 1 週 | Syllabus / Chapter 1 Digital Systems and Binary Numbers |
| 第 2 週 | 2/28 Peace Memorial Day (no class) 3/1 Meichu Game (no class) |
| 第 3 週 | Chapter 2 Boolean Algebra and Logic Gates |
| 第 3 週 | Chapter 2 Boolean Algebra and Logic Gates |
| 第 4 週 | 3/13 Chapter 2 Boolean Algebra and Logic Gates 3/15 Chapter 3 Gate-Level Minimization |
| 第 4 週 | 3/13 Chapter 2 Boolean Algebra and Logic Gates 3/15 Chapter 3 Gate-Level Minimization |
| 第 5 週 | 3/20 Chapter 3 Gate-Level Minimization 3/22 Business Trip (no class) |
| 第 5 週 | 3/20 Chapter 3 Gate-Level Minimization 3/22 Business Trip (no class) |
| 第 6 週 | Chapter 3 Gate-Level Minimization / Exam #1 |
| 第 6 週 | Chapter 3 Gate-Level Minimization / Exam #1 |
| 第 7 週 | Spring Vacation (no class) |
| 第 8 週 | 4/10 Exam 1 4/12 Chapter 4 Combinational Logic |
| 第 8 週 | 4/10 Exam 1 4/12 Chapter 4 Combinational Logic |
| 第 9 週 | Chapter 4 Combinational Logic |
| 第 9 週 | Chapter 4 Combinational Logic |
| 第 10 週 | 4/24 Chapter 4 Combinational Logic 4/26 Chapter 5 Synchronous Sequential Logic |
| 第 10 週 | 4/24 Chapter 4 Combinational Logic 4/26 Chapter 5 Synchronous Sequential Logic |
| 第 11 週 | Chapter 5 Synchronous Sequential Logic |
| 第 11 週 | Chapter 5 Synchronous Sequential Logic |
| 第 12 週 | 5/8 Chapter 5 Synchronous Sequential Logic Chapter 6 Registers ad Counters |
| 第 12 週 | 5/8 Chapter 5 Synchronous Sequential Logic Chapter 6 Registers ad Counters |
| 第 13 週 | 5/15 Exam 2 5/17 Chapter 6 Registers ad Counters |
| 第 13 週 | 5/15 Exam 2 5/17 Chapter 6 Registers ad Counters |
| 第 14 週 | 5/22 Chapter 6 Registers ad Counters Chapter 7 Memory and Programmable Logic |
| 第 14 週 | 5/22 Chapter 6 Registers ad Counters Chapter 7 Memory and Programmable Logic |
| 第 15 週 | Chapter 7 Memory and Programmable Logic |
| 第 15 週 | Chapter 7 Memory and Programmable Logic |
| 第 16 週 | Exam 3 |
教科書
M. Morris Mano , Michael Ciletti, Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6/e (Global Edition), Pearson FT Press
Office Hours
- 地點
- EC125C
- 時間
- By appointment.
- 聯絡方式
- tsaimh@cs.nycu.edu.tw