高階系統晶片設計
Advanced SOC Design
| 節 | 週三 |
|---|---|
7 15:30–16:20 | 高階系統晶片設計 ED203（光復） 3 節連堂 |
8 16:30–17:20 | |
9 17:30–18:20 |
* 根據陽明交大上課時間表所列
This course follows the SOC Design course, based on a self-developed IC validation platform (FSIC – Full-Stack IC). Participants will design an application accelerator, integrate it into SoC, validate it with FPGA, and go through IC physical implementation and signoff flow. The course equips participants with the skills and knowledge required to become full-stack IC designers, able to handle all development stages from front-end design, back-end implementation, system debugging, and embedded programming. Upon completion of the course, students will be able 1. Learn Advanced topics in IC Design, SOC chip-level design 2. Develop an Application Accelerator 3. Complete IC design flow, and be ready for tape out.
Prerequisite Course: SOC Design
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Seven labs Midterm Final Projects
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| 週次 | 主題 |
|---|---|
| 第 1 週 | Course plan; FISC Architecture introduction |
| 第 2 週 | Catapult HLS - I |
| 第 3 週 | Catapult HLS - II |
| 第 4 週 | Advanced HLS Topics - Memory, Best Practice, Architecture Exampels |
| 第 5 週 | Chip Design Overview |
| 第 6 週 | Design for Test |
| 第 7 週 | Lab Presentation: fsic-sim, catapult-hls |
| 第 8 週 | Low Power Design |
| 第 9 週 | SOC Components - I |
| 第 10 週 | SOC Components - II |
| 第 11 週 | Synopsys Tool I - Design Compiler, VCS, Primetime |
| 第 12 週 | Synopsys Tools - StartRC, ICC2, ICV |
| 第 13 週 | Midterm |
| 第 14 週 | Advanced STA |
| 第 15 週 | Verification |
| 第 16 週 | Final Project Presentation |
Reference material will be given after each class
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