8/24 – 9/18

115-1 選課時程

進行中

  • 初選第一階段 6/15 – 6/18
  • 初選第二階段 6/22 – 6/25
  • 校際選修 進行中 8/24 – 9/18
  • 初選第三階段 8/31 – 9/3
  • 開學後加退選 9/7 – 9/21
  • 逾期加退選 9/21 – 9/24
選課資源

加入行事曆

選擇訂閱 Google Calendar,或下載通用的 ICS 檔案。

使用 Google Calendar 時,Google 會收到這份課表的公開連結。

進階電子設計自動化

Advanced EDA Topics

學期
112-2
學分
0 學分
當期課號
539002
永久課號
IIPS30021
開課單位
前瞻半導體研究所
授課教師
林柏宏
校區
光復
類別
選修
上課時間表
週三
5
13:20–14:10
進階電子設計自動化
ED202(光復)
3 節連堂
6
14:20–15:10
7
15:30–16:20

* 根據陽明交大上課時間表所列

概述

This course will explore a wide spectrum of advanced EDA topics that span from fundamental geometric data structures for chip layouts to emerging trends in hardware security. It covers several important topics, including large-scale ECO routing, RDL routing in 3D ICs , optical routing in NoCs, analog layout synthesis, DFM and hotspot detection, advanced logic synthesis and verification, and EDA for hardware security. This course adopts a holistic approach, combining theoretical knowledge with practical implementation. Programming assignments, group projects, and case studies will provide you with a practical understanding of the concepts discussed in the lectures.

先修科目

Python/C/C++ programming (mandatory), Data structures (nice to have), Algorithms or AI/ML (nice to have), VLSI design (nice to have), Introduction to EDA (nice to have)

備註

無備註

教學方式

教師未提供此項資料

評分方式

Programming labs 60% Quiz/Exam 20% Term project 20%

課程大綱
  • Geometric data structures for chip layouts
  • Large-scale ECO routing
  • RDL routing in 3D ICs
  • Optical routing in NoCs
  • Analog layout synthesis
  • Layout synthesis with FinFETs
  • DFM & Hotspot detection
  • Advanced logic synthesis and verification
  • EDA for Hardware security
  • Introduction
週次計畫
週次主題
第 1 週Introduction
第 2 週Geometric data structures for chip layouts KD-tree, R-tree, Cornerstitching, Voronoi diagram, Delaunay triangulation
第 3 週Geometric data structures for chip layouts KD-tree, R-tree, Cornerstitching, Voronoi diagram, Delaunay triangulation
第 4 週Large-scale ECO routing
第 5 週Large-scale ECO routing
第 6 週RDL routing in 3D ICs
第 7 週RDL routing in 3D ICs
第 8 週Optical routing for NoCs
第 9 週Optical routing for NoCs
第 10 週Analog layout synthesis Circuit structure analysis, analog placement, analog routing, P&R for RFICs
第 11 週Analog layout synthesis Circuit structure analysis, analog placement, analog routing, P&R for RFICs
第 12 週Analog layout synthesis Circuit structure analysis, analog placement, analog routing, P&R for RFICs
第 13 週Layout synthesis with FinFETs
第 14 週DFM & Hotspot detection
第 15 週Advanced logic synthesis and verification
第 16 週EDA for Hardware security
教科書

Refence books: 1.Electronic Design Automation by Wang, Chang, and Cheng 2.Electronic design automation for IC implementation, circuit design, and process technology: circuit design, and process technology by Lavagno, Markov, Martin, and Scheffer

Office Hours
地點
EF369 or Webex
時間
By appointment
聯絡方式
mphlin@nycu.edu.tw