類比混合訊號電路設計特論
Special topics in analog mixed-signal circuit design
| 節 | 週五 |
|---|---|
6 14:20–15:10 | 類比混合訊號電路設計特論 EC122（光復） 3 節連堂 |
7 15:30–16:20 | |
8 16:30–17:20 |
* 根據陽明交大上課時間表所列
This course will introduce the fundamentals of various ADC/Wireline architectures. The content will cover the building blocks of ADC/Wireline and their non-idealities in practical circuits. Students will practice the design flow, starting with Matlab modeling, followed by circuit simulation with ideal blocks, and then replacing parts of these blocks with real circuits.
Microelectronics, Circuit theories, Introduction to analog integrated circuits
無備註
Reference: 1. Behzad Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2001. 2. Behzad Razavi, “Principles of Data Conversion System Design,” Wiley-IEEE Press, 1994.
Midterm exam 15%, Final exam 15%, Homework 40%, Final project 30%
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| 週次 | 主題 |
|---|---|
| 第 1 週 | Introduction to Course Content and Rating Rules Analog-to-Digital Data Converter (ADC) Overview |
| 第 2 週 | ADC Performance Indexes and Flash ADC |
| 第 3 週 | Sampling Theory and SAR ADC |
| 第 4 週 | Oversampling and Noise Shaping |
| 第 5 週 | 停課 |
| 第 6 週 | 國慶日 |
| 第 7 週 | Delta-Sigma Modulator |
| 第 8 週 | 光復節補假 |
| 第 9 週 | Pipelined ADC and Digital Calibration |
| 第 10 週 | Midterm Examination (ADC) |
| 第 11 週 | High-Speed Links Overview -SerDes standards and link sequence -Noise and signaling |
| 第 12 週 | High-Speed Links Circuits and Systems -Receiver circuits: AFE, DFE, adaptive algorithm |
| 第 13 週 | High-Speed Links Circuits and Systems -Receiver circuits: CDR, De-Multiplexer |
| 第 14 週 | High-Speed Links Circuits and Systems -Transmitter circuits: Driver, Multiplexer, FIR EQ |
| 第 15 週 | Phase-Locked Loop (PLL) -Introduction of PLL -Building Blocks in PLL |
| 第 16 週 | Phase-Locked Loop (PLL) -Phase noise and jitter -PLL Implementation and Simulation |
| 第 17 週 | Final Examination (High-Speed Links/PLL) |
| 第 18 週 | Final Project Report (ADC or High-Speed Links/PLL) |
| 第 19 週 | (If schedule delayed ) |
| 第 20 週 | (If schedule delayed) |
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