超大型積體電路設計導論
Introduction to VLSI Design
| 節 | 週三 |
|---|---|
9 17:30–18:20 | 超大型積體電路設計導論 ED103（光復） 3 節連堂 |
A 18:30–19:20 | |
B 19:30–20:20 |
* 根據陽明交大上課時間表所列
本課程教授超大型積體電路（VLSI）設計之基礎知識，內容涵蓋 CMOS之 電晶體特性、邏輯閘與連線、組合與循序電路，以及加法器、乘法器等運算單元，同時亦介紹記憶體設計，以及 I/O、封裝、功耗與時脈等相關主題，並涵蓋低功耗設計與可測試性設計，最後將簡介 FinFET VLSI 技術。 本課程之目標在於讓學生學習超大型積體電路設計所需之核心知識，並透過使用TSRI所提供的EDA軟體 進行HSPICE 與 Verilog電路模擬練習，建立 VLSI 設計基礎，同時培養學生對 VLSI 設計的興趣與實務能力。 This course provides an introduction to Very Large-Scale Integration (VLSI) design. Students begin by learning the basic characteristics of CMOS transistors, logic effort, and interconnect behavior, followed by hands-on HSPICE simulation exercises. The course then covers combinational and sequential circuits, various circuit families, and datapath components such as adders and multipliers, which are practiced using Verilog-based design methods. Memory design topics, including SRAM, CAM, ROM, and PLA, are also introduced. The course further includes system-level topics such as PLLs, I/O, packaging, power delivery, and clock distribution. Students will also learn basic techniques for low-power design and design for testability. The course concludes with an overview of FinFET technology and other modern VLSI circuits. The objective of this course is to provide students with a foundation in VLSI design through a combination of theoretical concepts and hands-on practice using HSPICE and Verilog, and to help them develop both interest and practical skills for VLSI design.
建議先修過邏輯設計、電路學、及電子學(I) 或相關課程，具備相關基礎知識 Logic design, basic circuit theory, and basic microelectronics
無備註
教師未提供此項資料
- 期中考: 30% - 期末考: 30% - 作業/小考: 40% （學期成績將依實際分數分佈進行最後調整）
教師未提供此項資料
| 週次 | 主題 |
|---|---|
| 第 1 週 | Course Overview and Introduction |
| 第 2 週 | CMOS Circuits and Layout |
| 第 3 週 | CMOS Transistor Theory |
| 第 4 週 | Logic Effort and Interconnects |
| 第 5 週 | SPICE Simulation (模擬練習 #1) |
| 第 6 週 | Combinational Circuits |
| 第 7 週 | Circuit Families |
| 第 8 週 | Sequential Circuits |
| 第 9 週 | 期中考Mid-Term Exam |
| 第 10 週 | Adders and Datapath |
| 第 11 週 | Verilog Simulation (模擬練習 #2) |
| 第 12 週 | SRAM, CAM, ROM, and PLA |
| 第 13 週 | I/O, Packaging, Power, and Clock |
| 第 14 週 | Design for Low Power and Testability |
| 第 15 週 | FinFET VLSI |
| 第 16 週 | 期末考Final-Term Exam * 教學進度會依實際情況作調整 |
CMOS VLSI Design, A Circuits and Systems Perspective, Neil Weste and David Harris; Pearson; 第4版 (2010年 3月 1日), ISBN-10 : 0321547748
- 地點
- ED103
- 時間
- Wednesday: 4:40PM-5:30PM (請先email跟老師預約時間)
- 聯絡方式
- ccyang@niar.org.tw